Protocol Latency: MIPS and Reality

This paper describes several techniques designed to improve protocol latency, and reports on their effectiveness when measured on a modern RISC processor—the DEC Alpha. We found that memory bandwidth—whichhas long been known to dominate network throughput—is also a key factor in protocol latency. The techniques are designed to increase the effectiveness of the instruction-cache and result in reduced processor stall rates. Department of Computer Science The University of Arizona Tucson, AZ 85721 This work supported in part by ARPA Contract DABT63-91-C-0030, by Digital Equipment Corporation.